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Hongkong
Shenzhen
Shanghai
Hong Kong
1. Responsible for the development and maintenance of deep neural learning algorithms for medical instruments, including data cleaning, model optimization, embedded GPU transplantation optimization, performance evaluation, etc.;
2. Responsible for the system architecture design of the deep learning processing pipeline, cooperate with the algorithm team to integrate and optimize the target system;
3. Responsible for writing relevant technical documents, and coordinating test engineers to develop and test test cases.
1、Master degree or above in computer science, electronic information, software or related professional and technical background,
2、At least 2 years of experience in software development.
3、Master the basic methods of computer vision & machine learning, with strong algorithm implementation ability.
4、Proficient in C / C + +, data structure and design mode, with good software engineering habits.
5、Proficient in GPU programming, such as OpenCL, CUDA, etc.; master the optimization methods for common technical problems such as parallel algorithm processing and memory usage.
6、Strong learning ability, strong hands-on ability, familiar with the use of oscilloscope, logic analyzer and other related test instruments.
7、Strong sense of responsibility, strong sense of teamwork, have to deal with complex problems independently.
8、Priority should be given to those with strong research ability, strong code ability, rich relevant experience, or from well-known laboratories in the fields of computer vision / machine learning / computer graphics and data mining.
上海 · 張江
1.負(fù)責(zé)硬件系統(tǒng)設(shè)計(jì)及相關(guān)文檔撰寫；參與硬件解決方案評(píng)估及器件選型；
2.負(fù)責(zé)電路原理圖，PCB設(shè)計(jì)，硬件調(diào)試及測(cè)試；
3.負(fù)責(zé)基于FPGA的控制系統(tǒng)架構(gòu)設(shè)計(jì)，模塊編寫，系統(tǒng)仿真驗(yàn)證；配合軟硬件工程師，優(yōu)化和調(diào)試FPGA硬件設(shè)計(jì)以滿足軟硬件接口需求；配合圖像算法在FPGA上的硬件加速實(shí)現(xiàn)和驗(yàn)證；
4.產(chǎn)品系統(tǒng)級(jí)測(cè)試與調(diào)試及參與EMC、安規(guī)測(cè)試；
5.參與硬件成本控制.風(fēng)險(xiǎn)控制和質(zhì)量控制。
1.自動(dòng)化、電子類、半導(dǎo)體技術(shù)相關(guān)專業(yè)，2年及以上工作經(jīng)驗(yàn)，具備扎實(shí)的數(shù)模電、電路理論基礎(chǔ)；
2.熟練使用EDA軟件進(jìn)行電路原理圖設(shè)計(jì)，可以自主設(shè)計(jì)Layout或者有對(duì)接外發(fā)layout工作的經(jīng)驗(yàn)；
3.熟悉STM32 、PIC等系列MCU，精通硬件電路設(shè)計(jì)和底層軟件設(shè)計(jì)；
4.掌握XILINX / ALTERA FPGA硬件結(jié)構(gòu)、設(shè)計(jì)流程及開(kāi)發(fā)工具；熟悉FPGA接口：SPI、IIC、GTX、LVDS、DDR3、BT1120，AXI4；熟悉常用圖像接口：MIPI CSI ;MIPI DSI ;DVP；熟練使用Verilog或VHDL語(yǔ)言的優(yōu)先；
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